AMD made the CPU interesting again on Tuesday. On November 10, the company announced general availability of its 6th Gen EPYC server processors, codenamed Venice, built on the new Zen 6 architecture and TSMC's 2nm-class process. The flagship chip packs 256 cores and 512 threads into a single socket, with a full gigabyte of L3 cache, and AMD is pitching the whole lineup at the AI agent workloads that now dominate data center demand. It is the first server CPU built on a 2nm-class node, and the first production server chip with PCIe Gen 6. And the first independent benchmarks are already arguing with each other.
What 256 cores actually buys you
The range is built around two kinds of chip. The density parts top out at the EPYC 9996, with 256 cores, 512 threads, a 4.1 GHz boost clock, 1,024 MB of L3 cache and a 600W power rating. The high-frequency parts trade cores for speed, with the fastest model offering 96 cores, a 4.05 GHz base clock and a 5.3 GHz boost. AMD says Zen 6 delivers a 31 percent uplift in instructions per clock for AI work over the previous Zen 5 generation, though ServeTheHome puts the IPC gain closer to 20 percent in its own testing. Either way, the core count is up from 192 in the previous Turin generation, and the cache has nearly tripled from 384 MB to a full gigabyte on the flagship.
The rest of the platform got a matching upgrade, because cores are only useful if you can feed them. Venice moves to 16 DDR5 memory channels per socket, up from 12, with up to 8 TB of memory per socket and peak bandwidth of about 1.6 TB/s using the fastest memory modules. It is also the first x86 server CPU with PCIe Gen 6, which doubles the bandwidth per lane compared with PCIe Gen 5 and matters a lot when the chip has to talk to racks full of GPUs. There is one catch for existing customers: the new chips use the SP7 socket, which is not backward compatible with the SP5 socket used by the Turin generation, so nobody is dropping a Venice chip into a server they already own. AMD announced no pricing with the launch, though a price list that surfaced in September puts the range at $700 to $14,904 for the flagship in 1,000-unit quantities.
The first tests are already arguing
AMD's own numbers are bold, and the first independent tests say some of them hold up and some of them do not. Tom's Hardware testing found a dual-socket system with two EPYC 9996 chips, 1,024 threads in total, delivered up to 93 percent higher performance than the previous generation in an estimated SPEC CPU 2026 integer-rate run, and Blender rendering ran 30 to 40 percent faster. But the same test day produced an awkward result in the opposite direction: in a ClickHouse database test, the 256-core flagship ran slower than the 192-core EPYC 9965 it replaces, a reminder that more cores do not win every workload and that memory-sensitive jobs can punish a design built for density.
AMD's marketing claims deserve the same careful reading. The company says Venice delivers up to 3.3 times more agents per watt than Nvidia's Vera CPU and 3.7 times the performance in integer tests, but those are AMD's own estimates, no independent lab has verified them yet, and the agents-per-watt figure leans on thread count as a stand-in for real agent work. AMD's own chip architects have said Venice was not designed specifically for agentic AI, even as the company's marketing leans hard into the agent era. That does not make the chip a disappointment, it makes the pitch a pitch. The honest version is that Venice is a very fast general-purpose server CPU that happens to be good at the work AI agents create, and the vendor claims are a starting point for the benchmarks, not the conclusion.
Who is buying, and what comes next
Servers with the new chips are already shipping from leading vendors including Quanta Cloud Technology, Lenovo, Hyve Solutions and Cornelis Networks, and cloud instances are close behind. Microsoft Azure is previewing HDv2 instances powered by the chips for AI data processing and high-performance computing, Oracle Cloud Infrastructure plans Compute E7 instances for enterprise workloads, and Meta is working with AMD as a lead customer and validating the platform for deployment at scale. Venice is only the first step in a wider Zen 6 rollout, with a smaller SP8 platform spanning 8 to 128 cores due in the first half of 2027, a cache-enhanced Venice-X variant coming in 2027, and low-power Verano variants expected in the second half of next year.
Venice is a real step forward, and the numbers that matter most are the ones nobody has to take AMD's word for. A 256-core chip on a 2nm-class process, the first production server CPU with PCIe Gen 6, shipping today with real generational gains in the workloads that scale with cores, that is a solid launch by any measure. The agent-era pitch is marketing running ahead of the evidence, and the database result is a useful warning that core count is not a score by itself. But the direction is clear enough: the CPU is back at the center of the AI data center conversation, and AMD just made sure Intel and Nvidia both have to answer it.
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Author: Alan Ward
Seattle News Desk